.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples/memory_constrained_scheduling.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code. .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_memory_constrained_scheduling.py: ========================================= Memory Constrained Scheduling ========================================= .. GENERATED FROM PYTHON SOURCE LINES 7-19 .. code-block:: Python from b_asic.architecture import Architecture, Memory, ProcessingElement from b_asic.core_operations import ConstantMultiplication from b_asic.fft_operations import R2Butterfly from b_asic.list_schedulers import HybridScheduler from b_asic.schedule import Schedule from b_asic.scheduler import ASAPScheduler from b_asic.sfg_generators import radix_2_dif_fft from b_asic.special_operations import Input, Output sfg = radix_2_dif_fft(points=16) .. GENERATED FROM PYTHON SOURCE LINES 20-21 The SFG is .. GENERATED FROM PYTHON SOURCE LINES 21-23 .. code-block:: Python sfg .. raw:: html
%3 in0 in0 r2bfly0 r2bfly0 in0:e->r2bfly0 0 in1 in1 r2bfly1 r2bfly1 r2bfly0->r2bfly1 0 0 r2bfly2 r2bfly2 r2bfly0->r2bfly2 0 1 r2bfly15 r2bfly15 in1:e->r2bfly15 0 in2 in2 cmul8 cmul8 r2bfly15->cmul8 1 r2bfly14 r2bfly14 r2bfly15->r2bfly14 0 0 r2bfly22 r2bfly22 in2:e->r2bfly22 0 in3 in3 r2bfly21 r2bfly21 r2bfly22->r2bfly21 0 0 cmul16 cmul16 r2bfly22->cmul16 1 r2bfly29 r2bfly29 in3:e->r2bfly29 0 in4 in4 cmul5 cmul5 r2bfly29->cmul5 1 r2bfly28 r2bfly28 r2bfly29->r2bfly28 0 0 r2bfly31 r2bfly31 in4:e->r2bfly31 0 in5 in5 r2bfly31->r2bfly1 1 0 cmul0 cmul0 r2bfly31->cmul0 1 r2bfly13 r2bfly13 in5:e->r2bfly13 0 in6 in6 cmul9 cmul9 r2bfly13->cmul9 1 r2bfly13->r2bfly14 1 0 r2bfly23 r2bfly23 in6:e->r2bfly23 0 in7 in7 r2bfly23->r2bfly21 1 0 cmul15 cmul15 r2bfly23->cmul15 1 r2bfly30 r2bfly30 in7:e->r2bfly30 0 in8 in8 cmul6 cmul6 r2bfly30->cmul6 1 r2bfly30->r2bfly28 1 0 in8:e->r2bfly0 1 in9 in9 in9:e->r2bfly15 1 in10 in10 in10:e->r2bfly22 1 in11 in11 in11:e->r2bfly29 1 in12 in12 in12:e->r2bfly31 1 in13 in13 in13:e->r2bfly13 1 in14 in14 in14:e->r2bfly23 1 in15 in15 in15:e->r2bfly30 1 out0 out0 out1 out1 r2bfly25 r2bfly25 r2bfly25->out0:w 0 out8 out8 r2bfly25->out8:w 1 out2 out2 r2bfly11 r2bfly11 r2bfly11->out1:w 0 out9 out9 r2bfly11->out9:w 1 out3 out3 r2bfly18 r2bfly18 r2bfly18->out2:w 0 out10 out10 r2bfly18->out10:w 1 out4 out4 r2bfly5 r2bfly5 r2bfly5->out3:w 0 out11 out11 r2bfly5->out11:w 1 out5 out5 r2bfly26 r2bfly26 r2bfly26->out4:w 0 out12 out12 r2bfly26->out12:w 1 out6 out6 r2bfly12 r2bfly12 r2bfly12->out5:w 0 out13 out13 r2bfly12->out13:w 1 out7 out7 r2bfly19 r2bfly19 r2bfly19->out6:w 0 out14 out14 r2bfly19->out14:w 1 r2bfly6 r2bfly6 r2bfly6->out7:w 0 out15 out15 r2bfly6->out15:w 1 r2bfly20 r2bfly20 r2bfly1->r2bfly20 0 1 r2bfly24 r2bfly24 r2bfly1->r2bfly24 0 0 r2bfly3 r2bfly3 r2bfly2->r2bfly3 0 0 r2bfly4 r2bfly4 r2bfly2->r2bfly4 0 1 cmul0->r2bfly2 1 r2bfly3->r2bfly11 0 0 r2bfly3->r2bfly12 0 1 r2bfly4->r2bfly5 0 0 r2bfly4->r2bfly6 0 1 cmul1 cmul1 cmul1->r2bfly4 1 cmul2 cmul2 cmul2->r2bfly6 1 r2bfly7 r2bfly7 r2bfly7->r2bfly5 1 0 r2bfly7->cmul2 1 cmul3 cmul3 cmul3->r2bfly7 0 cmul4 cmul4 cmul4->r2bfly7 1 r2bfly8 r2bfly8 r2bfly8->cmul4 1 r2bfly9 r2bfly9 r2bfly8->r2bfly9 1 0 cmul5->r2bfly8 0 cmul6->r2bfly8 1 r2bfly9->r2bfly11 1 0 cmul7 cmul7 r2bfly9->cmul7 1 r2bfly10 r2bfly10 r2bfly10->cmul3 1 r2bfly10->r2bfly9 0 0 cmul7->r2bfly12 1 cmul8->r2bfly10 0 cmul9->r2bfly10 1 r2bfly16 r2bfly16 r2bfly14->r2bfly16 0 0 cmul10 cmul10 r2bfly14->cmul10 1 r2bfly16->r2bfly25 1 0 cmul14 cmul14 r2bfly16->cmul14 1 r2bfly17 r2bfly17 cmul10->r2bfly17 0 r2bfly17->r2bfly18 1 0 cmul12 cmul12 r2bfly17->cmul12 1 cmul11 cmul11 cmul11->r2bfly17 1 cmul12->r2bfly19 1 r2bfly20->r2bfly18 0 0 r2bfly20->r2bfly19 0 1 cmul13 cmul13 cmul13->r2bfly20 1 r2bfly21->cmul13 1 r2bfly21->r2bfly24 1 0 r2bfly24->r2bfly25 0 0 r2bfly24->r2bfly26 0 1 cmul14->r2bfly26 1 r2bfly27 r2bfly27 cmul15->r2bfly27 1 r2bfly27->r2bfly3 1 0 r2bfly27->cmul1 1 cmul16->r2bfly27 0 r2bfly28->r2bfly16 1 0 r2bfly28->cmul11 1


.. GENERATED FROM PYTHON SOURCE LINES 24-25 Set latencies and execution times. .. GENERATED FROM PYTHON SOURCE LINES 25-35 .. code-block:: Python sfg.set_latency_of_type(R2Butterfly, 3) sfg.set_latency_of_type(ConstantMultiplication, 2) sfg.set_execution_time_of_type(R2Butterfly, 1) sfg.set_execution_time_of_type(ConstantMultiplication, 1) # # %% # Generate an ASAP schedule for reference schedule1 = Schedule(sfg, scheduler=ASAPScheduler()) schedule1 .. raw:: html
2026-06-03T14:26:38.818394 image/svg+xml Matplotlib v3.10.9, https://matplotlib.org/


.. GENERATED FROM PYTHON SOURCE LINES 36-37 Generate a PE constrained HybridSchedule .. GENERATED FROM PYTHON SOURCE LINES 37-41 .. code-block:: Python resources = {R2Butterfly.type_name(): 1, ConstantMultiplication.type_name(): 1} schedule2 = Schedule(sfg, scheduler=HybridScheduler(resources)) schedule2 .. raw:: html
2026-06-03T14:26:39.299895 image/svg+xml Matplotlib v3.10.9, https://matplotlib.org/


.. GENERATED FROM PYTHON SOURCE LINES 42-46 .. code-block:: Python direct, mem_vars = schedule2.get_memory_variables().split_on_length() print("Max read ports:", mem_vars.read_ports_bound()) print("Max write ports:", mem_vars.write_ports_bound()) .. rst-class:: sphx-glr-script-out .. code-block:: none Max read ports: 3 Max write ports: 3 .. GENERATED FROM PYTHON SOURCE LINES 47-71 .. code-block:: Python operations = schedule2.get_operations() bfs = operations.get_by_type_name(R2Butterfly.type_name()) bfs.show(title="R2Butterfly executions") const_muls = operations.get_by_type_name(ConstantMultiplication.type_name()) const_muls.show(title="ConstMul executions") inputs = operations.get_by_type_name(Input.type_name()) inputs.show(title="Input executions") outputs = operations.get_by_type_name(Output.type_name()) outputs.show(title="Output executions") bf_pe = ProcessingElement(bfs, entity_name="bf") mul_pe = ProcessingElement(const_muls, entity_name="mul") pe_in = ProcessingElement(inputs, entity_name='input') pe_out = ProcessingElement(outputs, entity_name='output') mem_vars = schedule2.get_memory_variables() mem_vars.show(title="All memory variables") direct, mem_vars = mem_vars.split_on_length() mem_vars.show(title="Non-zero time memory variables") mem_vars_set = mem_vars.split_on_ports( read_ports=1, write_ports=1, total_ports=2, strategy="greedy_graph_color" ) .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_001.png :alt: R2Butterfly executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_001.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_002.png :alt: ConstMul executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_002.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_003.png :alt: Input executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_003.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_004.png :alt: Output executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_004.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_005.png :alt: All memory variables :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_005.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_006.png :alt: Non-zero time memory variables :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_006.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 72-82 .. code-block:: Python memories = [] for i, mem in enumerate(mem_vars_set): memory = Memory(mem, memory_type="RAM", entity_name=f"memory{i}") memories.append(memory) mem.show(title=f"{memory.entity_name}") memory.assign("greedy_graph_color") memory.show_content(title=f"Assigned {memory.entity_name}") direct.show(title="Direct interconnects") .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_007.png :alt: memory0 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_007.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_008.png :alt: Assigned memory0 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_008.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_009.png :alt: memory1 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_009.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_010.png :alt: Assigned memory1 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_010.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_011.png :alt: memory2 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_011.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_012.png :alt: Assigned memory2 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_012.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_013.png :alt: Direct interconnects :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_013.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 83-90 .. code-block:: Python arch = Architecture( {bf_pe, mul_pe, pe_in, pe_out}, memories, direct_interconnects=direct, ) arch .. raw:: html
%3 cluster_memories Memories cluster_pes Processing Elements cluster_io_in Inputs cluster_io_out Outputs memory0 0 memory0 : (RAM, 5 cells) 0 _wl_out_0 memory0 memory0:e->_wl_out_0 memory1 0 memory1 : (RAM, 5 cells) 0 _wl_out_4 memory1 memory1:e->_wl_out_4 memory2 0 memory2 : (RAM, 2 cells) 0 _wl_out_8 memory2 memory2:e->_wl_out_8 bf 0 bf 0 1 1 _wl_out_11 bf_0 bf:e->_wl_out_11 _wl_out_21 bf_1 bf:e->_wl_out_21 mul 0 mul 0 _wl_out_17 mul mul:e->_wl_out_17 input input 0 inputout0_branch input:e->inputout0_branch output 0 output memory1_in0_mux 0 memory1_in0_mux 0 1 2 3 memory1_in0_mux:e->memory1:w bf_in1_mux 0 bf_in1_mux 0 1 2 bf_in1_mux:e->bf:w memory2_in0_mux 0 memory2_in0_mux 0 1 2 memory2_in0_mux:e->memory2:w memory0_in0_mux 0 memory0_in0_mux 0 1 2 3 memory0_in0_mux:e->memory0:w bf_in0_mux 0 bf_in0_mux 0 1 2 3 4 bf_in0_mux:e->bf:w output_in0_mux 0 output_in0_mux 0 1 2 3 output_in0_mux:e->output:w inputout0_branch->memory1_in0_mux:w inputout0_branch->bf_in1_mux:w inputout0_branch->memory2_in0_mux:w inputout0_branch->memory0_in0_mux:w _wl_in_1 memory0 _wl_in_1:e->bf_in0_mux:w _wl_in_2 memory0 _wl_in_2:e->output_in0_mux:w _wl_in_3 memory0 _wl_in_3:e->bf_in1_mux:w _wl_in_5 memory1 _wl_in_5:e->bf_in0_mux:w _wl_in_6 memory1 _wl_in_6:e->bf_in1_mux:w _wl_in_7 memory1 _wl_in_7:e->output_in0_mux:w _wl_in_9 memory2 _wl_in_9:e->output_in0_mux:w _wl_in_10 memory2 _wl_in_10:e->bf_in0_mux:w _wl_in_12 bf_0 _wl_in_12:e->memory1_in0_mux:w _wl_in_13 bf_0 _wl_in_13:e->bf_in0_mux:w _wl_in_14 bf_0 _wl_in_14:e->memory0_in0_mux:w _wl_in_15 bf_0 _wl_in_15:e->output_in0_mux:w _wl_in_16 bf_0 _wl_in_16:e->memory2_in0_mux:w _wl_in_18 mul _wl_in_18:e->bf_in0_mux:w _wl_in_19 mul _wl_in_19:e->memory1_in0_mux:w _wl_in_20 mul _wl_in_20:e->memory0_in0_mux:w _wl_in_22 bf_1 _wl_in_22:e->mul:w _wl_in_23 bf_1 _wl_in_23:e->memory2_in0_mux:w _wl_in_24 bf_1 _wl_in_24:e->memory1_in0_mux:w _wl_in_25 bf_1 _wl_in_25:e->memory0_in0_mux:w


.. GENERATED FROM PYTHON SOURCE LINES 91-92 Generate another HybridSchedule but this time constrain the amount of reads and writes to reduce the amount of memories .. GENERATED FROM PYTHON SOURCE LINES 92-101 .. code-block:: Python resources = {R2Butterfly.type_name(): 1, ConstantMultiplication.type_name(): 1} schedule3 = Schedule( sfg, scheduler=HybridScheduler( resources, max_concurrent_reads=2, max_concurrent_writes=2 ), ) schedule3 .. raw:: html
2026-06-03T14:26:45.515826 image/svg+xml Matplotlib v3.10.9, https://matplotlib.org/


.. GENERATED FROM PYTHON SOURCE LINES 102-106 .. code-block:: Python direct, mem_vars = schedule3.get_memory_variables().split_on_length() print("Max read ports:", mem_vars.read_ports_bound()) print("Max write ports:", mem_vars.write_ports_bound()) .. rst-class:: sphx-glr-script-out .. code-block:: none Max read ports: 2 Max write ports: 2 .. GENERATED FROM PYTHON SOURCE LINES 107-128 .. code-block:: Python operations = schedule3.get_operations() bfs = operations.get_by_type_name(R2Butterfly.type_name()) bfs.show(title="R2Butterfly executions") const_muls = operations.get_by_type_name(ConstantMultiplication.type_name()) const_muls.show(title="ConstMul executions") inputs = operations.get_by_type_name(Input.type_name()) inputs.show(title="Input executions") outputs = operations.get_by_type_name(Output.type_name()) outputs.show(title="Output executions") bf_pe = ProcessingElement(bfs, entity_name="bf") mul_pe = ProcessingElement(const_muls, entity_name="mul") pe_in = ProcessingElement(inputs, entity_name='input') pe_out = ProcessingElement(outputs, entity_name='output') mem_vars.show(title="Non-zero time memory variables") mem_vars_set = mem_vars.split_on_ports( strategy="greedy_graph_color", read_ports=1, write_ports=1, total_ports=2 ) .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_014.png :alt: R2Butterfly executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_014.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_015.png :alt: ConstMul executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_015.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_016.png :alt: Input executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_016.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_017.png :alt: Output executions :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_017.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_018.png :alt: Non-zero time memory variables :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_018.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 129-139 .. code-block:: Python memories = [] for i, mem in enumerate(mem_vars_set): memory = Memory(mem, memory_type="RAM", entity_name=f"memory{i}") memories.append(memory) mem.show(title=f"{memory.entity_name}") memory.assign("greedy_graph_color") memory.show_content(title=f"Assigned {memory.entity_name}") direct.show(title="Direct interconnects") .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_019.png :alt: memory0 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_019.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_020.png :alt: Assigned memory0 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_020.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_021.png :alt: memory1 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_021.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_022.png :alt: Assigned memory1 :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_022.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_memory_constrained_scheduling_023.png :alt: Direct interconnects :srcset: /examples/images/sphx_glr_memory_constrained_scheduling_023.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 140-146 .. code-block:: Python arch = Architecture( {bf_pe, mul_pe, pe_in, pe_out}, memories, direct_interconnects=direct, ) arch .. raw:: html
%3 cluster_memories Memories cluster_pes Processing Elements cluster_io_in Inputs cluster_io_out Outputs memory0 0 memory0 : (RAM, 7 cells) 0 _wl_out_9 memory0 memory0:e->_wl_out_9 memory1 0 memory1 : (RAM, 7 cells) 0 _wl_out_4 memory1 memory1:e->_wl_out_4 mul 0 mul 0 _wl_out_14 mul mul:e->_wl_out_14 bf 0 bf 0 1 1 _wl_out_0 bf_1 bf:e->_wl_out_0 _wl_out_19 bf_0 bf:e->_wl_out_19 input input 0 inputout0_branch input:e->inputout0_branch output 0 output mul_in0_mux 0 mul_in0_mux 0 1 2 mul_in0_mux:e->mul:w memory0_in0_mux 0 memory0_in0_mux 0 1 2 3 memory0_in0_mux:e->memory0:w bf_in0_mux 0 bf_in0_mux 0 1 2 3 bf_in0_mux:e->bf:w memory1_in0_mux 0 memory1_in0_mux 0 1 2 3 memory1_in0_mux:e->memory1:w bf_in1_mux 0 bf_in1_mux 0 1 2 3 bf_in1_mux:e->bf:w output_in0_mux 0 output_in0_mux 0 1 2 output_in0_mux:e->output:w _wl_in_1 bf_1 _wl_in_1:e->memory1_in0_mux:w _wl_in_2 bf_1 _wl_in_2:e->memory0_in0_mux:w _wl_in_3 bf_1 _wl_in_3:e->mul_in0_mux:w _wl_in_5 memory1 _wl_in_5:e->bf_in0_mux:w _wl_in_6 memory1 _wl_in_6:e->bf_in1_mux:w _wl_in_7 memory1 _wl_in_7:e->mul_in0_mux:w _wl_in_8 memory1 _wl_in_8:e->output_in0_mux:w _wl_in_10 memory0 _wl_in_10:e->mul_in0_mux:w _wl_in_11 memory0 _wl_in_11:e->bf_in0_mux:w _wl_in_12 memory0 _wl_in_12:e->output_in0_mux:w _wl_in_13 memory0 _wl_in_13:e->bf_in1_mux:w _wl_in_15 mul _wl_in_15:e->bf_in1_mux:w _wl_in_16 mul _wl_in_16:e->bf_in0_mux:w _wl_in_17 mul _wl_in_17:e->memory1_in0_mux:w _wl_in_18 mul _wl_in_18:e->memory0_in0_mux:w inputout0_branch->memory0_in0_mux:w inputout0_branch->memory1_in0_mux:w inputout0_branch->bf_in1_mux:w _wl_in_20 bf_0 _wl_in_20:e->memory0_in0_mux:w _wl_in_21 bf_0 _wl_in_21:e->output_in0_mux:w _wl_in_22 bf_0 _wl_in_22:e->bf_in0_mux:w _wl_in_23 bf_0 _wl_in_23:e->memory1_in0_mux:w


.. rst-class:: sphx-glr-timing **Total running time of the script:** (0 minutes 11.292 seconds) .. _sphx_glr_download_examples_memory_constrained_scheduling.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: memory_constrained_scheduling.ipynb ` .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: memory_constrained_scheduling.py ` .. container:: sphx-glr-download sphx-glr-download-zip :download:`Download zipped: memory_constrained_scheduling.zip ` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_