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.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples/secondorderdirectformiir_architecture.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code. .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_secondorderdirectformiir_architecture.py: ========================================= Second-order IIR Filter with Architecture ========================================= .. GENERATED FROM PYTHON SOURCE LINES 7-33 .. code-block:: Python from b_asic.architecture import Architecture, Memory, ProcessingElement from b_asic.core_operations import Addition, ConstantMultiplication from b_asic.schedule import Schedule from b_asic.scheduler import ASAPScheduler from b_asic.sfg import SFG from b_asic.special_operations import Delay, Input, Output in1 = Input("IN1") c0 = ConstantMultiplication(5, in1, "C0") add1 = Addition(c0, None, "ADD1") T1 = Delay(add1, 0, "T1") T2 = Delay(T1, 0, "T2") b2 = ConstantMultiplication(0.2, T2, "B2") b1 = ConstantMultiplication(0.3, T1, "B1") add2 = Addition(b1, b2, "ADD2") add1.input(1).connect(add2) a1 = ConstantMultiplication(0.4, T1, "A1") a2 = ConstantMultiplication(0.6, T2, "A2") add3 = Addition(a1, a2, "ADD3") a0 = ConstantMultiplication(0.7, add1, "A0") add4 = Addition(a0, add3, "ADD4") out1 = Output(add4, "OUT1") sfg = SFG(inputs=[in1], outputs=[out1], name="Second-order direct form IIR filter") .. GENERATED FROM PYTHON SOURCE LINES 34-35 The SFG is .. GENERATED FROM PYTHON SOURCE LINES 35-37 .. code-block:: Python sfg .. raw:: html

.. GENERATED FROM PYTHON SOURCE LINES 38-39 Set latencies and execution times. .. GENERATED FROM PYTHON SOURCE LINES 39-44 .. code-block:: Python sfg.set_latency_of_type(ConstantMultiplication, 2) sfg.set_latency_of_type(Addition, 1) sfg.set_execution_time_of_type(ConstantMultiplication, 1) sfg.set_execution_time_of_type(Addition, 1) .. GENERATED FROM PYTHON SOURCE LINES 45-46 Create schedule. .. GENERATED FROM PYTHON SOURCE LINES 46-49 .. code-block:: Python schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True) schedule .. raw:: html

.. GENERATED FROM PYTHON SOURCE LINES 50-51 Reschedule to only require one adder and one multiplier. .. GENERATED FROM PYTHON SOURCE LINES 51-58 .. code-block:: Python schedule.move_operation('add3', 2) schedule.move_operation('cmul4', -4) schedule.move_operation('cmul3', -5) schedule.move_operation('cmul5', -2) schedule.move_operation('cmul2', 1) schedule .. raw:: html

.. GENERATED FROM PYTHON SOURCE LINES 59-60 Extract operations and create processing elements. .. GENERATED FROM PYTHON SOURCE LINES 60-75 .. code-block:: Python operations = schedule.get_operations() adders = operations.get_by_type_name('add') adders.show(title="Adder executions") mults = operations.get_by_type_name('cmul') mults.show(title="Multiplier executions") inputs = operations.get_by_type_name('in') inputs.show(title="Input executions") outputs = operations.get_by_type_name('out') outputs.show(title="Output executions") adder = ProcessingElement(adders, entity_name="adder") multiplier = ProcessingElement(mults, entity_name="multiplier") pe_in = ProcessingElement(inputs, entity_name='input') pe_out = ProcessingElement(outputs, entity_name='output') .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_001.png :alt: Adder executions :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_001.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_002.png :alt: Multiplier executions :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_002.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_003.png :alt: Input executions :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_003.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_004.png :alt: Output executions :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_004.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 76-77 Extract and assign memory variables. .. GENERATED FROM PYTHON SOURCE LINES 77-93 .. code-block:: Python mem_vars = schedule.get_memory_variables() mem_vars.show(title="All memory variables") direct, mem_vars = mem_vars.split_on_length() mem_vars.show(title="Non-zero time memory variables") mem_vars_set = mem_vars.split_on_ports(read_ports=1, write_ports=1, total_ports=2) memories = [] for i, mem in enumerate(mem_vars_set): memory = Memory(mem, memory_type="RAM", entity_name=f"memory{i}") memories.append(memory) mem.show(title=f"{memory.entity_name}") memory.assign("left_edge") memory.show_content(title=f"Assigned {memory.entity_name}") direct.show(title="Direct interconnects") .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_005.png :alt: All memory variables :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_005.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_006.png :alt: Non-zero time memory variables :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_006.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_007.png :alt: memory0 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_007.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_008.png :alt: Assigned memory0 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_008.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_009.png :alt: memory1 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_009.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_010.png :alt: Assigned memory1 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_010.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_011.png :alt: memory2 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_011.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_012.png :alt: Assigned memory2 :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_012.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_secondorderdirectformiir_architecture_013.png :alt: Direct interconnects :srcset: /examples/images/sphx_glr_secondorderdirectformiir_architecture_013.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 94-95 Create architecture. .. GENERATED FROM PYTHON SOURCE LINES 95-99 .. code-block:: Python arch = Architecture( {adder, multiplier, pe_in, pe_out}, memories, direct_interconnects=direct ) .. GENERATED FROM PYTHON SOURCE LINES 100-101 The architecture can be rendered in enriched shells. .. GENERATED FROM PYTHON SOURCE LINES 101-102 .. code-block:: Python arch .. raw:: html

.. rst-class:: sphx-glr-timing **Total running time of the script:** (0 minutes 1.498 seconds) .. _sphx_glr_download_examples_secondorderdirectformiir_architecture.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: secondorderdirectformiir_architecture.ipynb ` .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: secondorderdirectformiir_architecture.py ` .. container:: sphx-glr-download sphx-glr-download-zip :download:`Download zipped: secondorderdirectformiir_architecture.zip ` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_