Contents Menu Expand Light mode Dark mode Auto light/dark, in light mode Auto light/dark, in dark mode Skip to content
B-ASIC documentation
Logo
B-ASIC documentation
  • Tutorial
    • Algorithmic Modelling
    • Simulation
    • Mapping to Hardware
    • Code Generation
  • Examples
    • Automatic scheduling with custom IO times
    • Connecting multiple SFGs
    • First-order IIR Filter with Simulation
    • Five-point Winograd DFT
    • Comparison with folding
    • Introduction example for the TSTE87 course
    • Automatic scheduling for different latency-offsets
    • LDLT matrix inversion algorithm
    • LTI System Analysis
    • LWDF first-order allpass section
    • Memory Constrained Scheduling
    • Scheduling and Pipelining/Retiming
    • Example SFG used for scheduling in the TSTE87 course
    • Second-order IIR Filter with Schedule
    • Second-order IIR Filter with Architecture
    • Third-order Bireciprocal LWDF
    • Three-point Winograd DFT
    • Two-tap FIR filter
  • API
    • Algorithmic Representations
      • b_asic.sfg
      • b_asic.signal
      • b_asic.sfg_generators
      • b_asic.graph_component
      • b_asic.operation
      • b_asic.port
      • b_asic.state_space
      • b_asic.transfer_function
    • Operation Libraries
      • b_asic.core_operations
      • b_asic.special_operations
      • b_asic.utility_operations
      • b_asic.wdf_operations
      • b_asic.fft_operations
    • Simulation
      • b_asic.simulation
      • b_asic.signal_generator
      • b_asic.quantization
      • b_asic.data_type
    • Scheduling
      • b_asic.schedule
      • b_asic.scheduler
      • b_asic.list_schedulers
    • Resource Assignment and Architecture
      • b_asic.process
      • b_asic.resources
      • b_asic.resource_assigner
      • b_asic.architecture
    • Code generation
      • HDL Generation
        • b_asic.code_printer.vhdl
      • Testbench Generation
    • GUI
      • SFG GUI
      • Scheduler GUI
      • GUI Utilities
    • Research functions
    • Utilities
      • b_asic.utils
      • b_asic.save_load_structure
  • Publications
  • Contributing
Back to top
View this page

Resource Assignment and ArchitectureΒΆ

Modules for representing operations and memory variables, assigning them to hardware, and describing the resulting architecture.

  • b_asic.process
  • b_asic.resources
  • b_asic.resource_assigner
  • b_asic.architecture
Next
b_asic.process
Previous
b_asic.list_schedulers
Copyright © 2020-2026, Oscar Gustafsson et al
Made with Sphinx and @pradyunsg's Furo