Testbench Generation

Testbench generation using the B-ASIC toolbox.

Two testbench printers are available:

• CocotbPrinter — generates a cocotb testbench (Python).

• VhdlTbPrinter — generates a VHDL testbench.

Both printers take simulation results produced by simulating schedule.sfg and drive the generated architecture with the correct input stimuli, optionally asserting expected output values.

CocotbPrinter

class b_asic.tb_printer.cocotb.cocotb_printer.CocotbPrinter(sim_results: Mapping[ResultKey, Sequence[int | float | complex | DTypeLike | APyFixed | APyCFixed | APyFloat | APyCFloat]])

Class for generating cocotb test benches.

Parameters:

sim_resultsResultArrayMap

Simulation results mapping graph IDs to their output values over iterations. Must be obtained by simulating schedule.sfg, not the original SFG.

print(arch: Architecture, schedule: Schedule, *, path: str | Path = PosixPath('.'), simulator: str = 'ghdl', waves: bool = False, gui: bool = False, csv: bool = False, asserts: bool = True, io_registers: bool = False, enable_pin: bool = True) → None

Generate the cocotb test bench files.

Parameters:

archArchitecture

The architecture to generate the testbench for.

scheduleSchedule

The schedule used to build the architecture. Required to determine the timing of inputs and outputs for the testbench.

pathstr or Path, default Path()

The output directory path, defaults to the current directory.

simulatorstr, default “ghdl”

The simulator to use (e.g., “ghdl”, “nvc”).

wavesbool, default False

Whether to dump waveforms when running the testbench.

guibool, default False

Whether to launch the simulator GUI when running the testbench. If the simulator lacks a GUI, a waveform viewer will be launched, if possible.

csvbool, default False

Whether to dump input and output values to a CSV file during simulation.

assertsbool, default True

Whether to include output assertions in the testbench.

io_registersbool, default False

Whether the design was built with I/O registers. When True, output assertions are offset by 2 cycles.

enable_pinbool, default True

Whether the DUT has an en enable pin. When False, no enable signal is driven in the testbench.

VhdlTbPrinter

class b_asic.tb_printer.vhdl.vhdl_tb_printer.VhdlTbPrinter(sim_results: Mapping[ResultKey, Sequence[int | float | complex | DTypeLike | APyFixed | APyCFixed | APyFloat | APyCFloat]])

Class for generating VHDL test benches.

Parameters:

sim_resultsResultArrayMap

Simulation results mapping graph IDs to their output values over iterations.

print(arch: Architecture, dt: DataType, *, path: str | Path = PosixPath('.'), asserts: bool = True, io_registers: bool = False, enable_pin: bool = True, warmup_laps: int = 0, abs_tol: float | None = None, rel_tol: float | None = None) → None

Generate the VHDL test bench file.

Parameters:

archArchitecture

The architecture to generate the testbench for.

dtDataType

The data type used for port widths in signal declarations.

pathstr or Path, default Path()

The output directory path, defaults to the current directory.

assertsbool, default True

Whether to include output assertions in the testbench.

io_registersbool, default False

Whether the design was built with I/O registers. When True, output assertions are offset by 2 cycles.

enable_pinbool, default True

Whether the DUT has an en enable pin. When False, no en signal is declared and the port map omits the connection.

warmup_lapsint, default 0

The number of warm-up laps to include in the testbench.

abs_tolfloat or None, default None

Absolute tolerance for output assertions. When set (together with or instead of rel_tol), assertions use ieee.float_pkg real comparisons instead of exact bit patterns.

rel_tolfloat or None, default None

Relative tolerance for output assertions. Combined with abs_tol as max(abs_tol, rel_tol * abs(expected)).