Code Generation

Code generation using the B-ASIC toolbox.

One code printer is currently available:

  • VhdlPrinter — generates a VHDL implementation of an architecture.

VhdlPrinter

class b_asic.code_printer.vhdl.vhdl_printer.VhdlPrinter(dt: DataType, vhdl_2008: bool = False)

Generate VHDL source files for an Architecture.

Parameters:
dtDataType

Data type configuration used for generated VHDL.

vhdl_2008bool, default: False

Enable VHDL-2008 specific output where applicable.

get_compile_order(arch: Architecture) → list[str]

Return the file names for the VHDL code describing the provided architecture.

Parameters:
arch

Architecture instance used to determine the compile order of the generated VHDL files.

print(arch: Architecture, *, path: str | Path = PosixPath('.'), vhdl_ls: bool = False, **kwargs) → None

Write VHDL files for an Architecture.

Parameters:
archArchitecture

Architecture instance to generate code for.

pathstr | Path, optional

Output directory. Defaults to the current directory.

vhdl_lsbool, default False

Also write a vhdl_ls.toml configuration file for the VHDL Language Server alongside the generated VHDL files.

**kwargs

Optional VHDL code-generation settings. For info, see Notes.

Notes

Recognised keyword arguments, grouped by the component they affect:

Top-level / architecture

io_registersbool, default False

Insert registers on all top-level I/O ports.

multiplexer_control_registeredbool, default False

Register multiplexer control signals in generated top-level.

enable_pinbool, default True

Whether to include an enable pin on the top-level entity.

Processing elements

fp_backendstr or dict[str, str]

Floating-point IP backend to use. Pass a string to apply the same backend to every PE, or a {entity_name: backend} dict to select on a per-PE basis.

pe_registersdict[str, tuple[int, int]]

Register split (pre, post) inserted around the operator of a PE. Keys are either the PE entity name or the PE type name.

control_cycledict

Clock cycle inside an operation at which each control signal becomes available.

pipeline_pe_controlbool, default False

Register PE control signals after generation.

Memories (RAM)

output_syncbool, default True

Place output registers after memory read.

external_schedule_counterbool, default True

Use an external schedule counter signal.

std_logic_vectorbool, default False

Use std_logic_vector data instead of signed/unsigned.

pipeline_mem_controlbool, default False

Register memory control signals after generation.

Memories (register-based)

external_schedule_counterbool, default True

Use an external schedule counter signal.

std_logic_vectorbool, default False

Use std_logic_vector data.

Internals